A single-piece charge-based model for the output conductance of MOS transistors

Author

Schneider, M.C. ; Galup-Montero, C. ; Filho, O. C Gouveia ; Cunha, A.I.A.

Author_Institution

Dept. of Electr. Eng., Univ. Fed. de Santa Catarina, Florianapolis, Brazil

Volume

1

fYear

1998

fDate

1998

Firstpage

545

Abstract

This paper presents a physically based model of the MOSFET output conductance. The drain current and the output conductance of the MOS transistor are accurately described by single-piece functions of the inversion charge densities at source and drain. Carrier velocity saturation, channel length modulation (CLM) and drain induced barrier lowering (DIBL) are included in a single-piece analytical model. The results can be readily applied for first order analog circuit hand calculation

Keywords

MOSFET; carrier mobility; electric admittance; inversion layers; semiconductor device models; MOS transistors; MOSFET output conductance; carrier velocity saturation; channel length modulation; drain current; drain induced barrier lowering; first order analog circuit hand calculation; inversion charge densities; output conductance; physically based model; single-piece charge-based model; Analog circuits; Analytical models; Bridge circuits; Circuit simulation; Electronic mail; Impact ionization; Interpolation; MOSFET circuits; Smoothing methods; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813381

Filename

813381