Delay-Balanced Smart Repeaters for On-Chip Global Signaling

Author

Weerasekera, Roshan ; Pamunuwa, Dinesh ; Li-Rong Zheng ; Tenhunen, Hannu

Author_Institution

Dept. of Electron., Software & Comput. Syst., KTH Sch. for Inf. & Commun. Technol., Kista

fYear

2007

fDate

6-10 Jan. 2007

Firstpage

308

Lastpage

313

Abstract

In this paper we propose a smart driver, whose drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a main driver and assistant driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. It is shown that in an UMC 0.18mum technology the potential peak power saving, for typical global wire lengths, can be as much 18% with a 12% jitter reduction over a traditional repeater for a data rate of 1Gb/s

Keywords

driver circuits; interference suppression; jitter; repeaters; 0.18 micron; 1 Gbits/s; assistant driver; delay-balanced smart repeaters; higher effective load capacitance; jitter reduction; lower effective load capacitance; main driver; on-chip global signaling; smart driver; Capacitance; Energy consumption; Integrated circuit interconnections; Jitter; Propagation delay; Repeaters; Signal design; Switches; System-on-a-chip; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-7695-2762-0

Type

conf

DOI

10.1109/VLSID.2007.62

Filename

4092063