Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC´s

Author

Ker, Ming-Dou ; Peng, Jeng-Jie ; Jiang, Hsin-Chin

Author_Institution

Nanoelectronics & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Taiwan

fYear

2003

fDate

17-20 March 2003

Firstpage

161

Lastpage

166

Abstract

For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35 μm 1P4M 3.3 V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC ICs.

Keywords

CMOS integrated circuits; MOSFET; electrostatic discharge; integrated circuit bonding; integrated circuit layout; integrated circuit packaging; integrated circuit testing; lead bonding; protection; system-on-chip; thermal shock; thermal stresses; 0.35 micron; 3.3 V; CMOS process; I/O cell layout area; NMOS devices; area-efficient I/O layout; bond pads layout patterns; bonding stress; high-pin-count SOC IC; inter-layer metals; layout verification; on-chip ESD protection devices; sub-bond pad MOSFET; temperature cycling tests; test chip; test structure; thermal shock tests; Bonding; CMOS process; Electric shock; Electrostatic discharge; Integrated circuit layout; MOS devices; MOSFET circuits; Temperature; Testing; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2003. International Conference on

Print_ISBN

0-7803-7653-6

Type

conf

DOI

10.1109/ICMTS.2003.1197455

Filename

1197455