Modelling of breakdown voltage in sub-micron SOI transistors

Model validation for submicron SIMOX (separation by implantation of oxygen) transistors by careful comparison of the simulated and measured snapback voltages as a function of gate length is reported. The transistors were fabricated in SIMOX material with an estimated film thickness of 0.2 μm, a buried insulator thickness of 0.4 μm, and a gate oxide thickness of 20 nm. The measured threshold voltage of the 1 μm n-channel transistor was 1.08 V and the subthreshold slope 86 mV/decade. The snapback voltage was defined as the maximum drain voltage at which the transistor turns off, when swept in the direction of decreasing gate voltage. Excellent agreement has been achieved over a range of transistor gate lengths down to 0.5 μm. Two-dimensional device simulation can be used to determine the optimum transistor structure by considering the factors associated with engineering both the source and drain regions with a view to maximizing the breakdown voltage