Memory-based reasoning implemented by wafer scale integration

The high robustness of memory-based reasoning (MBR), which is suitable for hardware implementation using wafer scale integration (WSI) technology, is demonstrated. A WSI MBR hardware design is proposed. Its robustness is evaluated by a WSI MBR simulator. The results show that defects or other fluctuations of device parameters have only minor impacts on the performances of the MBR. It is found that in order to obtain higher reasoning accuracy, the size of the MBR database is much more crucial than the computation resolution. The proposed WSI MBR processor takes advantage of benefits discovered in the simulation results.