DocumentCode
3435288
Title
Delay management for programmable video signal processors
Author
Smeets, M.L.G. ; Aarts, E.H.L. ; Essink, G. ; de Kock, E.A.
Author_Institution
Philips Res., Eindhoven, Netherlands
fYear
1997
fDate
17-20 Mar 1997
Firstpage
126
Lastpage
133
Abstract
We consider the problem of memory allocation for intermediate data in the mapping of video algorithms onto programmable video signal processors. The corresponding delay management problem is proved to be NP-hard. We present a solution strategy that decomposes the delay management problem into a delay minimization problem followed by a delay assignment problem. The delay minimization problem is solved with network flow techniques. The delay assignment problem is handled by a constructive approach. The performance of the combined approach is analyzed by means of a benchmark set of industrially relevant video algorithms
Keywords
computational complexity; digital signal processing chips; real-time systems; timing; video signal processing; NP-hard problem; benchmark set; constructive approach; delay assignment problem; delay management problem; delay minimization problem; intermediate data; memory allocation; network flow techniques; programmable video signal processors; video algorithms; Delay; Job shop scheduling; Memory management; Resource management; Signal analysis; Signal mapping; Signal processing; Signal processing algorithms; Streaming media; Video signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location
Paris
ISSN
1066-1409
Print_ISBN
0-8186-7786-4
Type
conf
DOI
10.1109/EDTC.1997.582345
Filename
582345
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