DocumentCode
3435342
Title
Systematic design of data converters
Author
Gielen, Georges
Author_Institution
Katholieke Universiteit Leuven, Belgium
fYear
2001
fDate
2001
Abstract
The author discusses the systematic design of data converters. The topics covered include: performance limits in analog designs; data converter design flow; architectural design; circuit design; and layout generation
Keywords
circuit layout CAD; data conversion; error compensation; integrated circuit design; monolithic integrated circuits; ADC; DAC; Mondriaan layout tool; architectural design; current source sizing; current-steering D/A converter; data converter design; dynamic performance; floorplanning; high-speed A/D converter; latch sizing; layout generation; performance limits; spatial errors compensation; Circuit synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. Tutorial Guide: ISCAS 2001. The IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-7113-5
Type
conf
DOI
10.1109/TUTCAS.2001.946967
Filename
946967
Link To Document