Proceedings 21st IEEE VLSI Test Symposium

fYear

2003

fDate

1-1 May 2003

Abstract

The following topics are dealt with: scan test; IP cores; test compaction; on-chip interconnect; IC test; current based test; open architecture ATE; built-in self-test; mixed-signal test; nanometer technologies; test data analysis; fault simulation; modular SoC testing; power consumption; core-based SoCs; layout driven design; high speed I/Os; data compression; memory testing; system-level test; diagnosis techniques; bridging faults; consumer products; and emerging circuit technologies.

Keywords

automatic test equipment; boundary scan testing; built-in self test; consumer electronics; data compression; fault diagnosis; fault simulation; integrated circuit interconnections; integrated circuit testing; integrated memory circuits; mixed analogue-digital integrated circuits; system-on-chip; very high speed integrated circuits; IC test; IP cores; bridging faults; built-in self-test; consumer products; core-based SoCs; current based test; data compression; diagnosis techniques; emerging circuit technologies; fault simulation; high speed I/Os; layout driven design; memory testing; mixed-signal test; modular SoC testing; nanometer technologies; on-chip interconnect; open architecture ATE; power consumption; scan test; system-level test; test compaction; test data analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2003. Proceedings. 21st

Conference_Location

Napa, CA, USA

ISSN

1093-0167

Print_ISBN

0-7695-1924-5

Type

conf

DOI

10.1109/VTEST.2003.1197622

Filename

1197622