• DocumentCode
    3435608
  • Title

    Shaping a VLSI wire to minimize Elmore delay

  • Author

    Fishburn, John P.

  • Author_Institution
    Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
  • fYear
    1997
  • fDate
    17-20 Mar 1997
  • Firstpage
    244
  • Lastpage
    251
  • Abstract
    Euler´s differential equation of the calculus of variations is used to determine the shape of a VLSI wire that minimizes Elmore delay. The solution is given as a power series whose coefficients are formulas involving the load-end wire width, the load capacitance, the capacitance per unit area, and the capacitance per unit perimeter. In contrast to an optimal-width rectangular wire, the RC Elmore delay of the optimally tapered wire goes to zero as the driver resistance goes to zero. The optimal taper is immune, to first order, to process variations affecting wire width
  • Keywords
    VLSI; capacitance; delays; differential equations; distributed parameter networks; integrated circuit interconnections; minimisation; transmission line theory; Elmore delay minimisation; Euler differential equation; RC Elmore delay; RC ladder; VLSI wire shaping; calculus of variations; capacitance per unit area; capacitance per unit perimeter; distributed RC line; load capacitance; load-end wire width; optimally tapered wire; power series; Calculus; Capacitance; Delay estimation; Delay lines; Differential equations; Geometry; Gravity; Shape; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Design and Test Conference, 1997. ED&TC 97. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1066-1409
  • Print_ISBN
    0-8186-7786-4
  • Type

    conf

  • DOI
    10.1109/EDTC.1997.582366
  • Filename
    582366