On the accuracy of Elmore-based Delay Models

We evaluate Elmore-based Interconnect Delay Models under nanoscale technology parameters. Due to a large delay overestimation Elmore delay provides at specific nodes, some attempts to provide more accurate models have been made. However, without reasonable parameters corresponding to actual cmos processes generations, the evaluation of the derived models is potentially dubitable. With technology parameters corresponding to the smaller feature sizes available, we evaluate the ac-curacy of Elmore-based delay models in nowadays VLSI scenarios. Besides an overview of the delay models behavior along technological scaling, we measure the different accuracy for intermediate/local and long/global interconnects.