On the trade-off between resolution time and delay times in bistable circuits

Flip flops used to store a bit in a register have different requirements to flip flops used in a synchronizer application. The D input must be held stable during the setup and until the Q output appears, these times determine the remaining part of the clock cycle available for computing. On the other hand the D input can violate setup and hold times in a synchronizer, and the reliability of the synchronizer depends on the metastability recovery time constant. We show how these parameters can be traded off in a simple edge triggered D flip flop and other cells.