• DocumentCode
    3436222
  • Title

    Test data compression using dictionaries with fixed-length indices [SOC testing]

  • Author

    Li, Lei ; Chakrabarty, Krishnendu

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
  • fYear
    2003
  • fDate
    27 April-1 May 2003
  • Firstpage
    219
  • Lastpage
    224
  • Abstract
    We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. The proposed method is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive a large number of internal scan chains in the circuit under test. Therefore, it is especially suitable for a reduced pin-count and low-cost DFT test environment, where a narrow interface between the tester and the SOC is desirable. The dictionary-based approach not only reduces testing time but it also eliminates the need for additional synchronization and handshaking between the SOC and the ATE. The dictionary entries are determined during the compression procedure by solving a variant of the well-known clique partitioning problem from graph theory. Experimental results for the ISCAS-89 benchmarks and representative test data from IBM show that the proposed method outperforms a number of recently-proposed test data compression techniques.
  • Keywords
    automatic test equipment; boundary scan testing; circuit simulation; data compression; design for testability; graph theory; integrated circuit design; integrated circuit testing; logic design; logic simulation; logic testing; system-on-chip; ATE channels; SOC testing time reduction; clique partitioning problem; compressed test patterns; dictionary-based test data compression; fixed-length index dictionaries; graph theory; internal scan chains; low-cost DFT; reduced pin-count DFT; test data volume reduction; tester/SOC interface; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Dictionaries; Graph theory; Logic testing; System-on-a-chip; Test data compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2003. Proceedings. 21st
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-1924-5
  • Type

    conf

  • DOI
    10.1109/VTEST.2003.1197654
  • Filename
    1197654