High performance Bulk FinFET with bottom spacer

Author

Tripathi, S.L. ; Mishra, Ravishankar ; Narendra, V. ; Mishra, R.A.

Author_Institution

Dept. of ECE, MNNIT, Allahabad, India

fYear

2013

fDate

17-19 Jan. 2013

Firstpage

1

Lastpage

5

Abstract

In this paper we propose a novel bottom spacer Bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. It solves the problem associated with the width quantization effect with optimized spacer height. Using well-calibrated device models and simulations, we have shown that Bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs using 3-D device simulation and design methodology.

Keywords

MOSFET; semiconductor device models; silicon-on-insulator; system-on-chip; 3D device simulation; SOI FinFET; SoC; bottom spacer; design methodology; high performance bulk FinFET structure; logic applications; optimized spacer height; system-on-chip; well-calibrated device models; width quantization effect; Doping profiles; FinFETs; Optimization; Performance evaluation; Quantization; Semiconductor process modeling; Bulk Fin-shaped field-effect transistor (FinFET); Sentarous TCAD device simulator; short-channel performance; spacer; width quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Computing and Communication Technologies (CONECCT), 2013 IEEE International Conference on

Conference_Location

Bangalore

Print_ISBN

978-1-4673-4609-2

Type

conf

DOI

10.1109/CONECCT.2013.6469282

Filename

6469282