Power efficient Networks on Chip

A low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduces the power consumption of the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover, the power reduction technique is applied to different NoC architectures. The technique reduces the power consumption of the network by up to 41%. When the power consumption of the whole network including the interswich links and repeaters is taken into account, the overall power consumption is decreased by up to 33% at the maximum operating frequency of the switch. The BFT architecture consumes the minimum power as compared to other NoC architectures.