A test interface for built-in test of non-isolated scanned cores

We consider the problem of built-in test pattern generation for non-isolated scanned cores. When two such cores are interconnected, a block of combinational logic that spans both cores may be created. Our goal is to provide a solution for built-in testing of logic that spans multiple cores. Starting from a given test-pattern generator (TPG), we propose a design-for-testability approach to improve the fault coverage achieved by the TPG. This approach is based on designing the interfaces between pairs of cores such that they support the testing of both cores. The proposed approach does not require any modifications to the cores themselves. In a vast majority of the benchmark circuits considered, the proposed approach results in 100% fault coverage.