Interconnection delay in very high-speed VLSI

Interconnection delay of VLSI has been a major bottleneck in the design of high-speed digital systems. The authors present a rigorous analysis of the signal propagation delay in VLSI circuits. They show that wire inductance is an important factor in determining the delay when the delay is in the subnanosecond range and that this delay cannot be well estimated by the conventional modeling of the interconnection by RC circuits. The effect of feature size scaling on circuit performance is also evaluated, and the inherent limitations on scaling due to interconnection delay is discussed. Finally, the relationship between the delay and the technology parameters, such as wire resistance, wire capacitance, wire inductance, wire width, wire length, and load capacitance is investigated to provide guidelines for the interconnection technology development