An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS

An analog-to-digital and time-to-digital converter using a common architecture (Time A/D converter TAD) is presented. Its resolutions for both analog-to-digital converter (ADC) mode and time-to-digital converter (TDC) mode are settable. The circuit structure is a completely digital circuit including a ring-shaped pulse-delay-line (RDL) driven by an input voltage V_in, along with an RDL synchronous counter, latch, and encoder. A prototype TAD-IC core of 0.044 mm² in a 0.18-μm digital CMOS achieved 3.1 mV/LSB (8-bit, 20-MS/s, 1.7 mW), 15 μV/LSB (16-bit, 100-kS/s, 1.3 mW) in ADC mode, and 126 ps/LSB (V_in = 1.8 V, 25-bit), 368 ps/LSB (V_in = 1.0 V, 25-bit) in TDC mode, respectively. As an actual example of high-resolution ADC, a radio-controlled clock (RCC) receiver IC prototype is implemented with a minimum detectable sensitivity of 0.7 μVrms.