DocumentCode
3437708
Title
The design of the VLSI image-generator ZaP
Author
Saeijs, Ronald W J J ; van Berkel, C.H.
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
fYear
1988
fDate
3-5 Oct 1988
Firstpage
163
Lastpage
166
Abstract
The authors present the design of `zoom and pan´ (ZaP), a complex 160K-transistor delay-insensitive VLSI circuit. ZaP generates images from structured geometric data with a performance of a million boxes per second. A VLSI program is derived from a formal specification of ZaP though stepwise refinement and decomposition. The subsequent silicon compilation is described briefly. It is concluded that ZaP demonstrates that the design of `systems on silicon´ can be seen as a VLSI-programming activity, to be carried out by system designers
Keywords
VLSI; circuit layout CAD; 160K-transistor delay-insensitive VLSI circuit; VLSI image-generator ZaP; VLSI program; decomposition; design; silicon compilation; stepwise refinement; structured geometric data; Circuits; Delay; Displays; Formal specifications; Image generation; Laboratories; Production; Silicon; Vehicles; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location
Rye Brook, NY
Print_ISBN
0-8186-0872-2
Type
conf
DOI
10.1109/ICCD.1988.25683
Filename
25683
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