Processor design using path programmable logic

Path programmable logic (PPL) is a VLSI design methodology that is very efficient in the implementation of systems consisting of random logic, counters, and finite-state machines. Previous designs have shown that PPL does not efficiently allow the implementation of bus-oriented designs, such as microprocessors, arithmetic processors, and DSP (digital signal processor) chips. The authors present solutions that enable these architectures to be implemented more efficiently. The solutions are the introduction of automated routing and placement tools as well as the description of sophisticated PPL library cells. The implementation of a RISC (reduced-instruction-set computer) processor is used as a case study to verify the effectiveness of these changes to the existing PPL methodology