Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

Author

Takatani, Hiroki ; Tanaka, Yuichi ; Fujita, Hideaki ; Oizono, Y. ; Nabeshima, Yuji ; Sudo, Toshio ; Sakai, Akihiko ; Uchiyama, S. ; Ikeda, Hinata

Author_Institution

Shibaura-Inst. of Technol., Tokyo, Japan

fYear

2012

fDate

9-11 Dec. 2012

Firstpage

185

Lastpage

188

Abstract

The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV´s) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.

Keywords

system-in-package; three-dimensional integrated circuits; 3D SiP; 3D system in package; PDN impedance; SSO noise; antiresonance peak; logic chip; memory chip; organic package substrate; power distribution network impedance; power supply disturbance; silicon interposer; simultaneous switching output buffer noise; stacked chips; through silicon vias; Impedance; Noise; Noise measurement; Semiconductor device measurement; Silicon; Substrates; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012 IEEE

Conference_Location

Taipei

Print_ISBN

978-1-4673-1444-2

Electronic_ISBN

978-1-4673-1445-9

Type

conf

DOI

10.1109/EDAPS.2012.6469419

Filename

6469419