Power efficient architecture for motion estimation using the QSDS-DIC algorithm

This paper presents a power efficient and low hardware cost architecture for motion estimation (ME) using a Quarter Sub-sampled Diamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC) algorithm. QSDS-DIC is a new algorithm for motion estimation and it is based on the Diamond Search algorithm and the sub-sampling technique. The aspect of reducing significantly the number of SAD (Sum of Absolute Differences) calculations enables the development of an efficient hardware design for the ME. Moreover, the Dynamic Iteration Control available to the architecture, allows that the desired throughput can be achievable with a restriction in the number of iterations. This aspect enables a power efficient architecture, since the number of clock cycles can be reduced by using DIC technique. The implemented architecture uses blocks of 16×16 samples and it was described in VHDL. Synthesis results are presented for TSMC 0.8 um CMOS standard cell. The architecture can reach real time for HDTV 1080 p with power consumptions of 39.92 mW.