Design of a high-speed arithmetic datapath

Author

Birman, M. ; Chu, G. ; Hu, L. ; McLeod, J. ; Bedard, N. ; Ware, F. ; Torban, L. ; Lim, C.M.

Author_Institution

Weitek, Sunnyvale, CA, USA

fYear

1988

fDate

3-5 Oct 1988

Firstpage

214

Lastpage

215

Abstract

This paper presents the implementation of a 64/32 bit floating-point datapath circuit (WTL3×64). This high-speed CMOS circuit integrates a 2 Kbit six-port register file, an independent 64/32-bit alu, a multiplier, and a divide/square-root unit for IEEE binary floating-point format numbers. It is fabricated using a 1.2 micron two-layer-metal CMOS technology. Operating at 60 ns cycle time, the 165000 transistor/147600 square mil chip provides 33 double-precision Mflops of peak performance. The register file, together with special registers, a flexible input/output interface, features for high level language support, and 1.5 Watts of power facilitate ease of integration of the device into various computer systems

Keywords

CMOS integrated circuits; VLSI; digital arithmetic; 1.2 micron; 32 bit; 33 MFLOPS; 64 bit; CMOS circuit; IEEE binary floating-point format numbers; alu; floating-point datapath circuit; high-speed arithmetic datapath; multiplier; register file; CMOS technology; Circuits; Clocks; Computer interfaces; Delay; Floating-point arithmetic; High level languages; Power engineering computing; Registers; USA Councils;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25693

Filename

25693