DocumentCode
3438035
Title
Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis
Author
Mitra, S.K. ; Chowdhury, A.R.
Author_Institution
Dept. of Comput. Sci. & Eng., Univ. of Dhaka, Dhaka, Bangladesh
fYear
2015
fDate
3-7 Jan. 2015
Firstpage
441
Lastpage
446
Abstract
Reversible logic attains the dominance in the realm of overwhelming research in logic synthesis and also has the significance in the context of quantum computing because of loss-less information processing. Due to low power dissipation, researchers are first designing smaller components with reversible gates, that eventually lead to design reversible computer. In this paper, we propose a robust architecture of logarithmic barrel shifter that performs bidirectional arithmetic and logical shifting, including rotate operation. Incorporating fault tolerance capability, the circuit is designed very efficiently that exhibits superior performance over state-of-the-art design methods in terms of minimum number of gates, garbage outputs, ancilla inputs, quantum cost, delay and others cost factors.
Keywords
arithmetic; fault tolerant computing; logic gates; network synthesis; optimisation; shift registers; threshold elements; bidirectional arithmetic; fault tolerance capability; logarithmic barrel shifter optimization; logical shifting; reversible gates; reversible logic synthesis; rotate operation; Bidirectional control; Complexity theory; Delays; Fault tolerance; Fault tolerant systems; Hardware; Logic gates; Ancilla Inputs; Delay; Garbage Outputs; Quantum Cost;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Type
conf
DOI
10.1109/VLSID.2015.80
Filename
7031774
Link To Document