A rule based logic reorganization system LORES/EX

Author

Ishikawa, J. ; Sato, H. ; Hiramine, M. ; Ishida, K. ; Oguri, S. ; Kazuma, Y. ; Murai, S.

Author_Institution

Mitsubishi Electr. Corp., Kanagawa, Japan

fYear

1988

fDate

3-5 Oct 1988

Firstpage

262

Lastpage

266

Abstract

The authors describe a rule-based logic reorganization system LORES/EX, which transforms an existing logic circuit into one that is dependent on other technology. The system can be not only flexibly adjustable to technology changes, but also has several special features as follows: (1) introduction of the circuit standardization rules makes the size of the rule base much smaller, and makes the description and modification of the rules easier; (2) application of conflict resolution based on evaluation functions contributes to the generation of high-quality circuits; and (3) introduction of the automatic partitioning of a circuit into subcircuits enables the reorganization of the circuit with some 10 K gates in a practical computation time

Keywords

logic CAD; LORES/EX; automatic partitioning; conflict resolution; logic circuit; rule based logic reorganization system; Application specific integrated circuits; Delay; Design engineering; Large scale integration; Logic circuits; Logic design; Production systems; Semiconductor devices; Standardization; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25703

Filename

25703