Designing self-testable multi-chip modules

This paper addresses the problem of Multi-Chip Module (MCM) testing, and specifically testing assembled MCM performance. The presented solution is based-on self-test. It augments the conventional single-chip BIST approach, which is needed to produce known-good-dies, to a new multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. This self-test mode not only provides detection of static and dynamic faults, but also identifies failed elements, i.e. bad dies or substrate. The multi-chip self-test scheme is based on a pseudo-random test approach and uses a multi-signature evaluation technique. The hardware design of multi-chip and single-chip self-test blocks are combined under a common architecture called the Dual BIST Architecture. The paper describes a set of design configurations to create Dual BIST Architecture. The presented BIST solution provides a reliable static and dynamic test at the module level as well as the bare die level