Striving toward correct FSMs: advances in design, formal verification, testing, and diagnosis

Finite-state machines (FSMs) in VLSI designs are discussed. FSMs are first classified according to different criteria. Various stages of their development are considered, namely design, formal verification, test pattern generation, and diagnosis. For each step, some novel approaches are identified and discussed. A unified approach, i.e. based on the same algorithm, to formally prove the equivalence of two FSMs, to generate test patterns, and to diagnose faults at the gate level, serves as a common denominator