Pandora-a microprogrammable node for DSP oriented architectures

The design and the performance evaluation of a parallel architecture for digital signal processing (DSP) are described. Many DSP applications cannot be efficiently solved by using standard DSP sequential microprocessors. In this case, using dedicated parallel architectures is the best way to obtain high performance, but they need flexibility to apply different DSP algorithms efficiently. The Pandora architecture provides a high degree of flexibility both for the system architecture (a mixed SIMD/MIMD technique is exploited) and for the node capability to implement different DSP algorithms (due to the writable control store). The node architecture and its VLSI implementation are described, focusing on the architectural aspects and the performance evaluation