Advanced scalable ultralow-k/Cu interconnect technology for 32 nm CMOS ULSI using self-assembled porous silica and self-aligned CoWP barrier

An advanced scalable Cu damascene process was developed using self-assembled porous silica with tetramethylcyclo-tetrasiloxane (TMCTS) treatment and selective electroless plating of Cu barrier. It is found that the TMCTS vapor treatment could recover process-induced damages after plasma ashing and chemical mechanical polishing, resulting in no line-width dependence of the effective dielectric constant of the porous silica films. Furthermore, the selective electroplating of CoWP on Cu interconnects could suppress Cu drift and improve time-dependent dielectric breakdown of the porous silica film