Modeling interprocessor communication in polymorphic processor arrays

Author

Baglietto, P. ; Maresca, M. ; Frisiani, A.L.

Author_Institution

DIST Genoa Univ., Italy

fYear

1991

fDate

13-16 May 1991

Firstpage

713

Lastpage

717

Abstract

A high-level model for interprocessor communication operations in polymorphic processor arrays (PPA) is presented. The interconnection network topology and the connection autonomy features of an SIMD massively parallel computer have great influence on its computational capabilities. The model is expressed in terms of procedures available in a function library of the PPC (polymorphic parallel C) language, which was developed for SIMD massively parallel programming. The PPA architecture, the PPC language, the interprocessor communication model, and an example of its use are presented

Keywords

cellular arrays; multiprocessor interconnection networks; parallel architectures; parallel languages; parallel programming; PPA architecture; PPC language; SIMD; connection autonomy; function library; interconnection network topology; interprocessor communication; massively parallel computer; massively parallel programming; polymorphic parallel C; polymorphic processor arrays; Computer architecture; Computer networks; Concurrent computing; Libraries; Multiprocessor interconnection networks; Network topology; Parallel algorithms; Parallel languages; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257478

Filename

257478