The application of compiler-assisted multiple-instruction retry to VLIW architectures

Author

Chen, Shyh-Kwei ; Fuchs, W.K. ; Hwu, Wen-Mei W.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

1994

fDate

12-14 Jun 1994

Firstpage

51

Lastpage

58

Abstract

Two compiler-assisted multiple-instruction word retry schemes for very long instruction word (VLIW) architectures are described. The first scheme compacts the compiler-generated hazard-free code with different degrees of rollback capability for scalar processors, and inserts no-ops in the scheduled code words. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards

Keywords

instruction sets; parallel architectures; program compilers; system recovery; VLIW architectures; compiler-assisted multiple-instruction retry; compiler-generated hazard-free code; data hazards; hardware read buffer; rollback capability; scalar processors; scheduled code words; very long instruction word architectures; Delay; Hardware; Hazards; NASA; Parallel processing; Processor scheduling; Registers; Software performance; Timing; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault-Tolerant Parallel and Distributed Systems, 1994., Proceedings of IEEE Workshop on

Conference_Location

College Station, TX

Print_ISBN

0-8186-6807-5

Type

conf

DOI

10.1109/FTPDS.1994.494474

Filename

494474