DocumentCode
3444892
Title
A buffer merging technique for reducing memory requirements of synchronous dataflow specifications
Author
Murthy, Praveen K. ; Bhattacharyya, Shuvra S.
Author_Institution
Angeles Design Syst., USA
fYear
1999
fDate
36465
Firstpage
78
Lastpage
84
Abstract
Synchronous Dataflow, a subset of dataflow has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem during software synthesis from SDF specifications is the minimization of the memory used by the target code. We develop a powerful formal technique called buffer merging that attempts to overlay buffers in the SDF graph systematically, in order to drastically reduce data buffering requirements. We give a polynomial-time algorithm based on this formalism, and show that code synthesized using this technique results in more than a 60% reduction of the buffering memory consumption compared to existing techniques
Keywords
buffer storage; data flow graphs; digital signal processing chips; formal specification; DSP program specification; SDF graph; SDF specifications; Synchronous Dataflow; buffer merging; buffer merging technique; buffering memory consumption; data buffering requirements; embedded DSPs; formal technique; memory minimization; memory requirements; polynomial-time algorithm; software synthesis; synchronous dataflow specifications; Computational modeling; Costs; Digital signal processing; Digital signal processing chips; Job shop scheduling; Merging; Optimizing compilers; Pipelines; Processor scheduling; Program processors;
fLanguage
English
Publisher
ieee
Conference_Titel
System Synthesis, 1999. Proceedings. 12th International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7695-0356-X
Type
conf
DOI
10.1109/ISSS.1999.814264
Filename
814264
Link To Document