A test structure for plasma process charging monitor in advanced CMOS technologies

Author

Kim, Sang U.

Author_Institution

Sematech, Austin, TX, USA

fYear

1996

fDate

20-23 Oct 1996

Firstpage

57

Lastpage

61

Abstract

In this report, a new plasma damage monitor for advanced CMOS technology with TOX <7 nm is introduced. The proposed damage monitor is very simple, most sensitive to plasma charging, and most of all, correlates to real circuit performance and reliability. The monitor is based on an unconventional antenna structure (a transistor with an isolated gate pad) combined with realistic antenna ratio and the gate oxide leakage measurement only. No other device parameters (Vt, Gm, Idsat, interface states, or QBD) measurements are required. No other antenna design is required. The plasma damage monitor can also be used for future ULSI CMOS manufacturing

Keywords

CMOS integrated circuits; ULSI; integrated circuit measurement; integrated circuit reliability; leakage currents; plasma applications; IC reliability; ULSI; advanced CMOS technologies; antenna ratio; antenna structure; circuit performance; damage monitor; gate oxide leakage measurement; plasma process charging monitor; Antenna measurements; CMOS technology; Circuit optimization; Circuit testing; Interface states; Isolation technology; Monitoring; Plasma devices; Plasma measurements; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop, 1996., IEEE International

Conference_Location

Lake Tahoe, CA

Print_ISBN

0-7803-3598-8

Type

conf

DOI

10.1109/IRWS.1996.583384

Filename

583384