Pipelined virtual camera configuration for real-time image processing based on FPGA

Real-time image processing is important for many application areas which require a quick response from events in a scene. Since real-time image processing involves large amount of computations, many approaches have been proposed to solve this problem especially using a dedicated hardware system. However, they are not sufficiently adapted to practical use because their dedicated hardware architecture is not suitable to carry out multiple tasks even in the case of a reconfigurable architecture. This paper proposes a pipelined virtual camera configuration which can perform several image processing tasks, especially at the low and intermediate levels, through the reconfiguration of the system. By synchronizing the entire system with the pixel clock, each processing modules can regard the others as a virtual camera. As a result, both the performance and the degree of reconfiguration are significantly increased.