A comparison of high frequency cell designs for high voltage DMOSFETs

To reduce the conduction and switching losses in a MOSFET, it is desirable to reduce its specific on-resistance (R_on,sp) and the specific input capacitance (C_in,sp). In this paper, the Atomic Lattice Layout (ALL) and the Circular Layout (CL) are compared for a high frequency 400 V n-channel MOSFET with the goal of obtaining the lowest R_onC_in product. The terrace gate design on ALL, with 6000 Å field oxide under the terrace gate region resulted in a R_onC_in product of 603 Ω-pf which is nearly 4 times lower than the conventional DMOS design. It was also found to be superior to the same gate design on a CL. In the cell structure with a floating P⁺ diffusion, the gate-drain component (C_gd) of the input capacitance (C_in) was reduced by moving the floating P⁺ diffusion edge closer to the P-base edge at the expense of increasing the on-resistance. By studying the variation of the R_onC_in product as a function of the position of the floating P⁺ edge, lowest R _onC_in products of 452 Ω-pf and 360 Ω-pf were obtained for the ALL and CL, respectively. Although the R_onC_in product of this structure is smaller than the terraced gate structures, the specific on-resistance is larger (98 mΩ-cm² vs 68 mΩ-cm² for the ALL and 137 mΩ-cm² vs 86 mΩ-cm² for the CL), which implies an increase in the die area. It was shown through simulations that the specific on-resistance did not increase appreciably with a reduction in the gate bias from 10 V to 5 V. Hence operation at 5 V gate bias is recommended to reduce the gate switching losses, which increase as the square of the gate drive voltage