Hardware/software partitioning with iterative improvement heuristics

Author

Eles, Petru ; Peng, Zebo ; Kuchcinski, Krzysztof ; Doboli, Alexa

Author_Institution

Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden

fYear

1996

fDate

6-8 Nov 1996

Firstpage

71

Lastpage

76

Abstract

The paper presents two heuristics for hardware/software partitioning of system level specifications. The main objective is to achieve performance optimization with a limited hardware and software cost. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria. One of the heuristics is based on simulated annealing and the other on tabu search. Experiments show the superiority of the tabu search based algorithm

Keywords

formal specification; logic CAD; real-time systems; simulated annealing; systems analysis; hardware/software partitioning; iterative improvement heuristics; minimization of communication cost; performance optimization; simulated annealing; system level specifications; tabu search; Application software; Cost function; Embedded system; Hardware; Information science; Iterative algorithms; Microprocessors; Partitioning algorithms; Simulated annealing; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

System Synthesis, 1996. Proceedings., 9th International Symposium on

Conference_Location

La Jolla, CA

ISSN

1080-1820

Print_ISBN

0-8186-7563-2

Type

conf

DOI

10.1109/ISSS.1996.565881

Filename

565881