Monotonic circuits with complete acknowledgement

Author

Starodoubtsev, Nikolai ; Bystrov, Sergei ; Yakovlev, Alex

Author_Institution

Tokyo Univ. of Social Welfare, Gunma, Japan

fYear

2003

fDate

12-15 May 2003

Firstpage

98

Lastpage

108

Abstract

The paper studies a class of asynchronous circuits in which every signal transition on the inputs of every gate is acknowledged during the circuit operation. This property is called complete acknowledgement (CA) and it is considered here for circuits that consist of gates described by monotonic Boolean functions only. In order to implement such circuits the standard CMOS designs of 2-input logic gates are modified by using an additional output for CA. The paper investigates the behavioral properties of monotonic CA (MCA) circuits and the feasibility of a behavioral specification to be refined to a CA-implementable form. The result of comparison of a number of CA realizations with their speed-independent counterparts produced by negative gate synthesis inspires optimism about the practicality of CA circuits. Being particularly robust to variations in technological parameters, e.g. the value and type of delay and switching thresholds, such circuits offer potential advantages for future CMOS designs.

Keywords

Boolean functions; CMOS logic circuits; asynchronous circuits; circuit analysis computing; logic CAD; 2-input logic gates; CMOS designs; asynchronous circuits; behavior-driven synthesis; behavioral specification; complete acknowledgement; monotonic Boolean functions; negative gate synthesis; signal transition acknowledgement; Asynchronous circuits; Boolean functions; CMOS logic circuits; CMOS technology; Circuit synthesis; Delay; Logic design; Logic gates; Robustness; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium on

ISSN

1522-8681

Print_ISBN

0-7695-1898-2

Type

conf

DOI

10.1109/ASYNC.2003.1199170

Filename

1199170