Efficient parallel searching with TCAMs

Author

Zhang, Bin ; Wu, Jianping ; Li, Qi ; Yang, Jiahai

Author_Institution

Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2010

fDate

16-18 June 2010

Firstpage

1

Lastpage

2

Abstract

Chip-level parallel TCAMs were deployed to circumvent the limitation of a single TCAM. In this paper, we propose a crossed address range division and integral caching scheme. We improve the update efficiency significantly by buddy update method while keep low power dissipation by decreasing the number of the triggered TCAMs access in each lookup operation. The lookup throughput is ultra high through adaptive load balance. Our simulation results show that the proposed scheme can achieve an average lookup speedup factor greater than 11 with 12 TCAM chips, given 10% more memory space.

Keywords

content-addressable storage; integrated circuits; parallel processing; semiconductor storage; table lookup; adaptive load balance; buddy update method; chip level parallel TCAM; crossed address range division; efficient parallel searching; integral caching; lookup throughput; low power dissipation; ternary content addressable memory; update efficiency; Bandwidth; Communication system traffic control; Computer science; Control theory; Downlink; Network topology; Relays; Spread spectrum communication; Traffic control; WiMAX;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality of Service (IWQoS), 2010 18th International Workshop on

Conference_Location

Beijing

ISSN

1548-615X

Print_ISBN

978-1-4244-5987-2

Type

conf

DOI

10.1109/IWQoS.2010.5542724

Filename

5542724