Neutron-induced soft error rate estimation for SRAM using PHITS

Author

Yoshimoto, Shusuke ; Amashita, Takuro ; Yoshimura, Masayoshi ; Matsunaga, Yusuke ; Yasuura, Hiroto ; Izumi, Shintaro ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko

Author_Institution

Kobe Univ., Kobe, Japan

fYear

2012

fDate

27-29 June 2012

Firstpage

138

Lastpage

141

Abstract

This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41% less than that of the general NMOS-PMOS-NMOS 6T cell layout.

Keywords

MOS integrated circuits; SRAM chips; integrated circuit layout; neutron effects; MCU; NMOS-PMOS-NMOS 6T version; PHITS; PMOS-NMOS-PMOS 6T SRAM cell layout; SER estimation tool; SEU; SRAM; data patterns; extracting function; horizontal multiple-cell-upset; inside-out PMOS-NMOS-PMOS versions; memory cell layout; neutron-induced soft error rate estimation; particle transport code; single-event-upset; vertical MCU SER; Atmospheric modeling; Error analysis; Layout; MOS devices; Neutrons; Random access memory; Single event upset; SRAM; multiple bit upset; neutron-induced soft error rate;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International

Conference_Location

Sitges

Print_ISBN

978-1-4673-2082-5

Type

conf

DOI

10.1109/IOLTS.2012.6313859

Filename

6313859