Using GPUs to accelerate FPGA wirelength estimate for use with complex search operators

As the precise wirelength for a given placement can only be known after routing, accurate and fast to compute wirelength estimates are required for FPGA placement algorithms. Two of the more effective wirelength estimation models are HPWL [1] and Star+ [2]. However, both of these models are expensive to compute requiring O(nm) time, where n is the number of nets and m is the average number of blocks to connect. In this paper, we show that the time to compute HPWL and Star+ can be reduced by as much as 577x and 548x, re spectively, by exploiting the computational power available in modern Graphical Processing Units (GPUs). To reduce the runtime required to compute HPWL and Star+ we propose a set of data structures targeted specifically for the GPU archi tecture. We then investigate five different mappings of these data structures to the GPU to determine which mapping best exploits the heterogeneous memories and thread-level parallelism available on the GPU. Though our results are geared towards FPGA placement, they extend naturally to the less constrained VLSI placement problem.