DocumentCode
3456975
Title
Polyhedral-Model Guided Loop-Nest Auto-Vectorization
Author
Trifunovic, Konrad ; Nuzman, Dorit ; Cohen, Albert ; Zaks, Ayal ; Rosen, Ira
Author_Institution
INRIA Saclay, Saclay, France
fYear
2009
fDate
12-16 Sept. 2009
Firstpage
327
Lastpage
337
Abstract
Optimizing compilers apply numerous interdependent optimizations, leading to the notoriously difficult phase-ordering problem - that of deciding which transformations to apply and in which order. Fortunately, new infrastructures such as the polyhedral compilation framework host a variety of transformations, facilitating the efficient exploration and configuration of multiple transformation sequences. Many powerful optimizations, however, remain external to the polyhedral framework, including vectorization. The low-level, target-specific aspects of vectorization for fine-grain SIMD has so far excluded it from being part of the polyhedral framework. In this paper we examine the interactions between loop transformations of the polyhedral framework and subsequent vectorization. We model the performance impact of the different loop transformations and vectorization strategies, and then show how this cost model can be integrated seamlessly into the polyhedral representation. This predictive modelling facilitates efficient exploration and educated decision making to best apply various polyhedral loop transformations while considering the subsequent effects of different vectorization schemes. Our work demonstrates the feasibility and benefit of tuning the polyhedral model in the context of vectorization. Experimental results confirm that our model has accurate predictions, providing speedups of over 2.0times on average over traditional innermost-loop vectorization on PowerPC970 and Cell-SPU SIMD platforms.
Keywords
computational geometry; parallel processing; Cell-SPU SIMD platforms; PowerPC970; compilers; decision making; fine-grain SIMD; phase-ordering problem; polyhedral compilation; polyhedral loop transformations; polyhedral representation; polyhedral-model guided loop-nest auto-vectorization; vectorization; Bridges; Concurrent computing; Context modeling; Cost function; Decision making; Optimizing compilers; Parallel architectures; Parallel processing; Predictive models; Production;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures and Compilation Techniques, 2009. PACT '09. 18th International Conference on
Conference_Location
Raleigh, NC
ISSN
1089-795X
Print_ISBN
978-0-7695-3771-9
Type
conf
DOI
10.1109/PACT.2009.18
Filename
5260526
Link To Document