Design of workload generator for modular hardware accelerator

Author

Hussin, Hanum Syahida ; Halim, Zaini Abdul

Author_Institution

Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Nibong Tebal, Malaysia

fYear

2011

fDate

4-7 Dec. 2011

Firstpage

138

Lastpage

143

Abstract

A modular hardware accelerator (MHA) is designed to provide a platform to interface with any computation algorithm (engine). The main blocks in MHA include a hardware accelerator adapter unit, scheduler unit, storage unit, power management unit, and workload generator (WG) unit. The current paper proposes a design of the WG for MHA. The WG unit will maintain the sequence of tasks that will be executed by the engine. The WG unit implements a 64-bit address bus, a 128-bit data bus, and a maximum request data length of 1024 double word to the main memory, with processing speed of 100 MHz.

Keywords

system-on-chip; 128-bit data bus; 64-bit address bus; MHA; computation algorithm; hardware accelerator adapter unit; modular hardware accelerator; power management unit; scheduler unit; storage unit; workload generator design; workload generator unit; Engines; Generators; Graphics; Hardware; Prefetching; Streaming media; Timing; hardware accelerator; modular hardware accelerator; workload generator;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Applications and Industrial Electronics (ICCAIE), 2011 IEEE International Conference on

Conference_Location

Penang

Print_ISBN

978-1-4577-2058-1

Type

conf

DOI

10.1109/ICCAIE.2011.6162120

Filename

6162120