DocumentCode
3458681
Title
Interaction between ILD-process and metal-etch induced gate charging effect
Author
Lin, Wallace ; Sery, George
Author_Institution
California Technol. & Manuf., Intel Corp., Santa Clara, CA, USA
fYear
2003
fDate
24-25 April 2003
Firstpage
16
Lastpage
19
Abstract
Interaction between ILD-process and metal-etch induced gate charging damage was investigated using via-intensive test structures and edge-intensive metal antenna structures. Strong interaction between the two effects was observed in multiple metal layer test structures. This interaction results in a marked turnaround behavior of the charging damage. This study also reveals that charging damage to gate oxide during via etch is dominated by the ILD deposition or etch process. This damage is independent of the number of vias but strongly depends on the relative position and the area of the metal holding the vias. The study also concludes that via-etch induced charging risk can be assessed by the metal area (to gate area) ratio rule DRC check at the layer of the metal holding the vias.
Keywords
CMOS integrated circuits; MOSFET; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; semiconductor device testing; sputter etching; surface charging; 5-metal-layer CMOS technology; ILD deposition; ILD process; N-MOSFETs; charging damage; edge-intensive metal antenna structures; gate oxide; metal area to gate area ratio rule; metal-etch induced gate charging damage; multiple metal layer test structures; via-etch induced charging risk; via-intensive test structures; Antenna measurements; Bonding; CMOS technology; Circuit testing; Etching; Integrated circuit interconnections; Integrated circuit measurements; MOSFET circuits; Manufacturing; Performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
Plasma- and Process-Induced Damage, 2003 8th International Symposium
Print_ISBN
0-7803-7747-8
Type
conf
DOI
10.1109/PPID.2003.1199720
Filename
1199720
Link To Document