Computation of two texture features in hardware

Author

Heikkinen, Katriina ; Vuorimaa, Petri

Author_Institution

Signal Process. Lab., Tampere Univ. of Technol., Finland

fYear

1999

fDate

1999

Firstpage

125

Lastpage

129

Abstract

This paper presents the hardware architectures of two texture features: mean and contrast. These features are based on the co-occurrence matrix method. However the features can be calculated without the co-occurrence matrix, too. The formalism behind the features without the co-occurrence matrix is shown, and the corresponding hardware architectures are depicted with data flow graphs (DFG). The architecture was developed with the very high speed integrated circuit Hardware Description Language (VHDL) and commercially available logic synthesis tool by Synopsys. The VHDL code was synthesized to Xilinx XC4000-series FPGA library

Keywords

data flow graphs; field programmable gate arrays; hardware description languages; image texture; matrix algebra; statistical analysis; FPGA library; Synopsys; VHDL; Very High Speed Hardware Description Language; Xilinx XC4000; co-occurrence matrix; contrast; data flow graphs; hardware architectures; logic synthesis tool; mean; texture features; Hardware; Image classification; Karhunen-Loeve transforms; Laboratories; Matrices; Mobile handsets; Pixel; Signal processing; Telecommunication computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Analysis and Processing, 1999. Proceedings. International Conference on

Conference_Location

Venice

Print_ISBN

0-7695-0040-4

Type

conf

DOI

10.1109/ICIAP.1999.797582

Filename

797582