A compact model of holding voltage for latch-up in epitaxial CMOS

From different fabrication processes down to 0.35 μm feature size and from two-dimensional device simulation, the holding voltage V _H for latch-up in epitaxial CMOS is found to be proportional to the square root of the holding current I_H, specially for V _H⩾2 V, while for V_H<2 V the V_H linearly follows the I_H. A slight modification of existing physically-based analytical models is set up for reproduction of all the observed dependencies, valid for different epitaxial layer thicknesses (t_epi) and different anode-to-cathode spacings (L), along with a self-consistent interpretation by exploring the role of the base pushout width (h). By incorporating a structure-oriented holding current formula to this modified model, a compact, closed-form expression for V _H is produced directly as a function of t_epi and L. The compact model can serve as the scaling law for the holding voltage down to 1 V. The potential application of the compact model to low voltage, low power CMOS integrated circuits for latchup free operation is also projected