• DocumentCode
    3461077
  • Title

    Overview of Dual rail with Precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors

  • Author

    Danger, Jean-Luc ; Guilley, Sylvain ; Bhasin, Shivam ; Nassar, Maxime

  • Author_Institution
    Dept. COMELEC, TELECOM ParisTech, Paris, France
  • fYear
    2009
  • fDate
    6-8 Nov. 2009
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    The security of cryptographic implementations relies not only on the algorithm quality but also on the countermeasures to thwart attacks aiming at disclosing the secrecy. These attacks can take advantage of leakages of the secret appearing through the power consumption or the electromagnetic radiations also called ¿Side Channels¿. This is for instance the case of the Differential Power Analysis (DPA) or the Correlation Power Analysis (CPA). Fault injections is another threatening attack type targeting specific nets in a view to change their value. The major principle to fight the side-channel attack consists in making the power consumption constant. The masking method allows the designer to get a power consumption which has a constant mean and a variance given by a random variable. Another manner is the Hiding method which consists in generating a constant power consumption by using a Dual-rail with Precharge phase Logic (DPL). This paper presents an overview of the various logic styles that have been promoted in the last six years, with an emphasis on their relative advantages and drawbacks.
  • Keywords
    cryptography; logic circuits; microprocessor chips; power consumption; correlation power analysis; differential power analysis; dual-rail precharge phase logic; fault injections; hardware cryptoprocessors; hiding method; implementation-level attacks; masking method; power consumption; side-channel attack; Cryptography; Design methodology; Electromagnetic radiation; Energy consumption; Hardware; Logic; Power generation; Rails; Random variables; Security; Differential Power Analysis; Dual-rail Precharge Logic; Fault Attacks; Side Channel Attacks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Circuits and Systems (SCS), 2009 3rd International Conference on
  • Conference_Location
    Medenine
  • Print_ISBN
    978-1-4244-4397-0
  • Electronic_ISBN
    978-1-4244-4398-7
  • Type

    conf

  • DOI
    10.1109/ICSCS.2009.5412599
  • Filename
    5412599