A Novel Post-Linearization Technique for Fully Integrated 5.5 GHz High-Linearity LNA

A novel post-linearization technique for fully integrated 5.5 GHz high-linearity LNA, implemented through a 0.18 ¿m RF CMOS technology, is demonstrated. The post-linearization technique adopts a folded cascode diode with a resistor and a capacitor in parallel as a third-order intermodulation distortion (IMD3) sinker. The LNA with the post-linearization technique has a +8.33 dBm IIP3, a power gain of 10.02 dB, and a noise figure of 3.05 dB, while consuming 6 mA from a supply voltage of 1.8 V. Comparison with the characteristics of the LNA without using post-linearization technique, the IIP3 is improved 6.21 dB, and the IMD3 can be reduced 12.77 dB. Moreover, the performances of noise figure and power consumption rise 0.09 dB and 0.08 mW, and the power gain lowers 0.3 dB after using the technique only. This technique indeed improves the linearity performance without obvious effects.