DocumentCode
3462453
Title
A Gain-Boosted Discrete-Time Charge-Domain FIR LPF with Double-Complementary MOS Parametric Amplifiers
Author
Yoshizawa, Atsushi ; Iida, Sachio
Author_Institution
Sony, Tokyo
fYear
2008
fDate
3-7 Feb. 2008
Firstpage
68
Lastpage
596
Abstract
Discrete-time charge-domain filters with FIR characteristics require the resetting of their sampling capacitors for every cycle.The gain boosting techniques presented in this paper are especially useful when applied to a high-order discrete-time charge-domain filter, where a multi-stage implementation is strongly preferred to obtain a large gain with appropriate circuit complexity. The chip is implemented in a 0.13 mum CMOS process. Implementation of the DCMPA for the discrete-time charge-domain filter is of practical significance as it easily provides the variable-gain capability. Triple wells are used to better isolate the DCMPAs from the clock pulse generator.
Keywords
CMOS integrated circuits; FIR filters; capacitors; discrete time filters; low-pass filters; parametric amplifiers; CMOS process; FIR filters; LPF; clock pulse generator; double-complementary MOS parametric amplifiers; gain boosting techniques; gain-boosted discrete-time charge-domain FIR; low-pass filter; multistage implementation; sampling capacitors; size 0.13 mum; triple wells; variable-gain capability; Boosting; Capacitance; Clocks; Finite impulse response filter; IIR filters; MOS devices; Sampling methods; Switches; Varactors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-2010-0
Electronic_ISBN
978-1-4244-2011-7
Type
conf
DOI
10.1109/ISSCC.2008.4523060
Filename
4523060
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