Strained-SOI (sSOI) technology for high-performance CMOSFETs in 45nm-or-below technology node

Author

Yoshimi, Makoto ; Cayrefourcq, Ian ; Mazuré, Carlos

Author_Institution

Soitec Asia, Inc., Tokyo

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

96

Lastpage

99

Abstract

Current status of strained-SOI (sSOI) substrate technology is reviewed along with relevant device-level strain optimization. Smart Cut trade enables to transfer a tensile-strained Si film, grown on Si_0.8Ge_0.2, onto a 300mm Si wafer, with excellent thickness uniformity and preserved stress. The pile-ups (PUs) have been eliminated and the threading dislocation density has been significantly reduced. Strained-Si film can be 80nm thick, making implementation of partially-depleted (PD) structure practical. The stress endures thermal treatment up to 1100 degree C, for 2 hours. Technology directions for PMOS improvement are discussed, including combination with uniaxial stress technologies

Keywords

MOSFET; nanoelectronics; silicon-on-insulator; 300 mm; 45 nm; 80 nm; CMOSFET; Smart Cut; partially-depleted structure; strained-SOI technology; substrate technology; uniaxial stress technology; CMOS technology; CMOSFETs; Capacitive sensors; Electron mobility; Germanium silicon alloys; MOS devices; Semiconductor films; Silicon germanium; Substrates; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306087

Filename

4098031