Power minimization of high-performance submicron CMOS circuits using a dual-V/sub dd/ dual-V/sub th/ (DVDV) approach

Author

Khellah, Muhammad M. ; Elmasry, M.I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

fYear

1999

fDate

17-17 Aug. 1999

Firstpage

106

Lastpage

108

Abstract

A new method, called DVDV, for low-power design of high-performance CMOS logic circuits is presented. DVDV utilizes a library of gates with dual supply voltages (V/sub dd/) and dual threshold voltages (V/sub th/) to achieve high-performance with minimum dynamic and leakage power. A Depth-First-Search (DFS) based heuristic for DVDV node assignment is described. Exercising the techniques on a set of benchmarks shows significant power savings over the dual-V, (with a single V/sub th/) scheme, and faster speeds than those possible with the dual-V/sub th/ (and a single V/sub dd/) approach.

Keywords

CMOS logic circuits; SPICE; circuit optimisation; circuit simulation; integrated circuit design; integrated circuit testing; logic CAD; low-power electronics; 0.25 mum; 1 to 2 V; DVDV node assignment; HSPICE simulation; benchmark circuit testing; depth-first-search based heuristic; dual supply voltages; dual threshold voltages; dual-V/sub dd/ dual-V/sub th/ approach; gate library; high-performance CMOS logic circuits; low-power design; minimum leakage power; power minimization; power savings; submicron CMOS circuits; Batteries; CMOS process; Circuits; Degradation; Delay; Design methodology; Libraries; Logic design; Minimization; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on

Conference_Location

San Diego, CA, USA

Print_ISBN

1-58113-133-X

Type

conf

Filename

799422