A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System

In contrast to the prior arts, this paper proposes a 14-band CMOS I/Q frequency synthesizer based on a single-PLL architecture. With proper frequency planning, only divide-by-2 dividers are needed in the feedback path of the PLL. Thus, more precise in- phase and quadrature phase sub-harmonics can be derived from the divider chain for SSB frequency mixing. On the other hand, the number of mixer stages in cascade is reduced to 2 for full- band carrier generation. Using a sub-harmonic I/Q calibration, the image spurs are suppressed below -45dBc and more than 33dB SFDR is achieved for the full band generation.